1. Field of the Invention
This invention relates to a control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system.
2. Description of the Related Art
A flash memory is available as one of the memories used with small information devices, machines, etc. The flash memory has the following four advantages as a promising memory replacing a hard disk:
1. Data is retained in a flash memory even if power is turned off (data in DRAM is lost when power is turned off).
2. Reading of data of a flash memory is relatively fast as compared with a hard disk.
3. A flash memory semiconductor device has good resistance to vibration as compared with that of a hard disk.
4. A flash memory is less expensive as compared with a SRAM.
However, the flash memory has the following disadvantages:
1. When data is written, the write area contents must have been erased.
2. Erasure is made in chip units or block units of a given size.
3. It takes time for a write operation to be implemented for reasons 1 and 2.
4. Since elements are degraded by repeating a write operation, the write count is limited.
FIG. 97 is a schematic diagram of a flash memory containing 1024 blocks each consisting of 512 bytes (524288 bytes in total). In FIG. 97, numeral 4110 denotes one block in the flash memory and numeral 4111 denotes a 1-byte data retention section in the block 4110, which will be hereinafter referred to as a cell. Numeral 4105 is a control circuit. When a read access is made to the flash memory, data is read from the cell determined by address signal A0-A8, a buffer 4121, and a decoder 4122 in the block determined by address signal A9-A18, a buffer 4131, and a decoder 4132, and is output via a register 4141 to I/O0-I/O7. Numeral 4123 is a control signal of the buffer 4121 and the decoder 4122. Numeral 4133 is a control signal of the buffer 4131 and the decoder 4132. Numeral 4142 is a control signal of the register 4141. On the other hand, when a write access is made to the flash memory in FIG. 97, the contents of the block determined by the address signal A9-A18, the buffer 4131, and the decoder 4132 are erased and input data from I/O0-I/O7 is written via the register 4141 into the cell determined by the address signal A0-A8, the buffer 4121, and the decoder 4122. Numeral 401 is a control signal of the controller 4105.
The limit of the write count mentioned above will introduce a serious problem with the use of the flash memory as storage media of a semiconductor disk. For example, data is written into areas such as a directory and FAT (file allocation table) on a disk more frequently than other areas, that is, data is frequently written into only specific blocks of the flash memory allocated to the directory and FAT and there is a good chance that the write count limit of the flash memory will be exceeded in the specific blocks faster than in other blocks. If the write count limit is exceeded, the elements are degraded and it may be impossible to carry out a normal read or write. If a directory or FAT on a disk is destroyed, the entire disk cannot be read. Therefore, malfunction only in specific blocks makes the entire semiconductor disk unusable, leading to poor efficiency.
A flash EEPROM (electrically erasable and programmable read only memory) system is described in Japanese Patent Laid-Open No.Hei 2-292798 as the related art of a file storage using a flash memory as storage media.
The related art provides a corrective action when a defective cell occurs in the flash memory. For example, the related art proposes that alternate cells are provided and that error correction control is performed so as to correct data disordered due to occurrence of a defective cell to normal data, whereby the write count limit as the disadvantage of the flash memory is overcome and the system life is extended. Also, the system is provided with a write cache memory and write back into the flash memory is executed based on the elapsed time from the last write into the cache memory. Data frequently rewritten is rewritten into the cache memory rather than the flash memory to reduce the operation of the flash memory in order to extend the over all system life.
In the error correction control, an error correction code is given for each sector (512 bytes), which is a storage unit of the flash memory conforming to a storage unit of the magnetic disk apparatus and when a data error occurs due to an element failure, it is detected and corrected based on the error correction code, thereby substantially increasing the number of times a write operation can be made. In the time monitor control of file rewrite, specifically the time until a once written file is next rewritten is monitored and if the file is not the longest unrewritten file, the data in the file is stored in a volatile buffer (cache memory) in order to reduce the substantial write count of the flash memory for frequently rewritten files such as a directory and FAT.
The idea is intended to ensure the practical life of a storage using the flash memory.
However, to use the error correction codes, it requires much time and enormous throughput to generate the codes and detect and correct errors, lowering performance and complicating circuitry.
Use of the volatile buffer memory (cache memory) is not intended for covering slow rewrite which is another disadvantage of the flash memory. Frequently rewritten files are stored in the cache memory, but a large file cannot be stored in the cache memory.
For example, a large file first written is written directly into a flash memory having slow write speed rather than a cache memory, thus a write access becomes slow. For large-capacity continuous data that can be accessed at high speed on a magnetic disk unit, the file system is very inferior to the magnetic disk unit in access performance.
In Japanese Patent Laid-Open No.Hei 5-204561 filed previously by the present applicant, to solve the problem, an alternate memory area is provided to prolong the semiconductor disk life. However, since the alternate memory area is previously allocated as a fixed area, once it runs out of space, additional alternate memory area becomes unavailable.
In addition, in Japanese Patent Laid-Open No.Hei 2-292798, data is transferred from the cache memory to the flash memory when extra space is required in the cache memory. However, when extra space is required, a request to store data may occur within the system, thus a write into the flash memory which is slow in rewriting would lower system performance.
As described above, control is intended to write frequently written data only into the cache memory, thus not all write data can be written at high speed. When a defective cell occurs on one sector, it takes time to perform the corresponding proper action. As a result, the data transfer time is prolonged and data transfer is delayed. Particularly, processing using the error correction code becomes complicated. The cache system in Japanese Patent Laid-Open No.Hei 2-292798 is provided to extend the system life. Although the technique about handling of cache data at data write is disclosed, no techniques about transfer of read data from the host which is an external system are disclosed. Therefore, the related art does not provide means accessible at high speed.
The main purpose of the related art is considered to replace magnetic disk units. The related art assumes an access in sector units via an external I/O bus provided for the system to transfer data to and from the external devices. However, it does not consider a random access from the CPU when the flash memory is used as the main memory, that is, direct data transfer in small units of several bytes, etc. The alternate cell method and error correction code processing are designed to transfer data in sector units; data cannot be transferred in byte or word units.
On the other hand, high-performance personal computers, etc., often use a DRAM-SRAM cache system as means for shortening the read or write time. Generally, the cache memory is located between the CPU and storage taking time to access for serving as a buffer memory. When the CPU reads the storage, the read address and data are stored in the cache memory. When the CPU then reads the same read address of the storage, the data corresponding to the address is obtained from the cache memory, thereby shortening the access time. The two systems of cache memory are known: Write through and copy back. The write through system is a system which rewrites the storage as well as the cache memory at the same time in response to a write request into a storage. On the other hand, the copy back system is a system which is responsive to a write request into a storage for rewriting only the cache memory without rewriting the storage which requires a lot of processing time and is intended to shorten the access time.
The cache memory system generally used with information processing systems such as personal computers at present includes the main memory of DRAM (dynamic random access memory) and a cache memory of SRAM (static random access memory) to cover the weak point that the DRAM access operation cannot keep up with the CPU operation speed. Accessed addresses are allocated to the SRAM and the DRAM accessed at slow speed is used to back up data as if the SRAM accessed at fast speed were the main memory when viewed from the CPU. In this technique, the SRAM access speed is several times as fast as the DRAM access speed, and although it is less than ten times as fast. Thus, when a write access is made to an address not allocated to the cache memory, namely, when write miss occurs, the recovery time is not so great. If the flash memory is adopted as the main memory, the flash memory has the rewrite time 1000 to 100000 times longer than the DRAM, and the recovery time at write miss becomes very great, lowering system performance. Therefore, this point must be considered when implementing a system.
To reduce flash memory chip costs, those skilled in the art focus attention on a cell structure for reducing the flash memory chip area. For example, a flash memory having a so-called NAND structure is adopted. In this structure, a line access rather than a random access is made and data is input/output in series in line units. For the future flash memory, it is considered that the line access system intended for high integration of memory will become the main stream. In addition, development of a memory adopting an access system similar to the line access system is pursued. Even if a memory of such a structure is used, it will become an important technology with regard to making random accesses at high speed. This point is not considered in the related art including Japanese Patent Laid-Open No.Hei 2-292798 discussed above.
Whether the main memory is volatile or nonvolatile makes a great system difference.
For example, when the main memory is volatile, if the system power is turned off with only the cache memory rewritten, data stored in both the main memory and the cache memory is cleared, introducing no problem. However, when the main memory is nonvolatile, if the power is turned off with the most recent data stored only in the cache memory, in fact the data just entered and still being considered by the user can disappear from the cache memory.
If the main memory of an information processing system is volatile, it is common practice to provide an auxiliary storage for saving file data. However, if the main memory system is nonvolatile, no auxiliary storage is required. (The main memory serves as a data save area.) This point is one of the merits of the system provided with the nonvolatile main memory, but it introduces a problem. For example, information processing systems may career out of control due to a program error or operator mistake. When this fault occurs, if the main memory is volatile, it is possible to reset the hardware or, as a last resort, temporarily turn off the power and restart the system, thereby clearing the main memory contents and again loading data into the main memory from the auxiliary storage for restoring the system to the normal state. However, if the main memory is nonvolatile, when the system careers out of control and data stored in the main memory is destroyed, correct data is lost and it is difficult to restore the system to the normal state.
Therefore, the information processing systems having a nonvolatile main memory must be provided with a corrective system for crashing of the processing system.
It is therefore an object of the invention to provide a file system using a high-performance and inexpensive flash memory as storage media.
Specifically, the file system life is prolonged without using a write buffer (cache memory) or error detection correction code.
A file system that can rewrite a flash memory at high speed is provided.
A file system which enables access to areas of data at high speed is provided.
A file system which suppresses deterioration of a flash memory by a simple configuration and simple processing is provided.
It is another object of the invention to dynamically change alternate storage areas for replacing degraded storage areas of a flash file system thereby further extending the life and to inform the user that alternate areas are no longer usable when no further alternate areas are available, thereby improving a user interface.
It is a further object of the invention to provide an information processing system having a flash memory as the main memory.
Specifically, a random access from the CPU is made possible.
Further, an information processing system which can support or is compatible with a high-integrated flash memory in a line access system is provided.
Further, the recovery time from a miss hit access is shortened for improving performance.
Further, action when the power is turned off is considered for improving reliability to prevent important data from being destroyed due to careening of control due to a program error or operator mistake, and after operation is stopped, access performance when operation is restarted is improved for enhancing total operability.
To these ends, according to the invention, there is provided a semiconductor file system comprising a first nonvolatile memory which is electrically erasable, a second nonvolatile memory which is not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed, the first nonvolatile memory storing data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory, the second nonvolatile memory previously storing interface information required for inputting and outputting the data from and to the external system and read-only data of the data, the controller including control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address, the control section responsive to the interface information, the first management information, and the second management information for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory, and the consecutive address generation means and the sector address storage means for outputting the physical sector address and the consecutively generated addresses to the first nonvolatile memory and the volatile memory when data at the physical sector address is output from the first nonvolatile memory or when data at the physical sector address is input to the volatile memory.
In the invention, the data store unit is made the same as one sector of hard disk. Data is always transferred in sector units to and from the host. To transfer the data at high speed, means for generating addresses at high speed is provided. To match the write speed with the high-speed address generation, the nonvolatile memory is used as a write buffer, and all write data is temporarily stored in the write buffer. The write buffer is used to temporarily save data. After data transfer from the host terminates, the data is transferred from the write buffer to the flash memory quickly. That is, the write buffer is not used to prolong the flash memory life and is used only for high-speed data transfer. The flash memory life is prolonged, for example, by managing the erasure count. The erasure count is recorded as the second management information in flash memory erasure units. How much the flash memory is degraded is decided according to the erasure count and write locations are determined for averaging progress of degradation. Thus, the erasure counts are recorded in the volatile memory used for the write buffer.
On the other hand, flash memory electrically erasable (first nonvolatile memory) and nonvolatile memory not electrically erasable (second nonvolatile memory), such as mask ROM or one-time PROM, are used as a memory to store data. The nonvolatile memory not electrically erasable is used as a memory to store interface information, such as the IC card internal configuration and access format.
Thus, when data is transferred from the host to the semiconductor file system, an address is generated matching with the data transfer speed of the host and is given to the volatile memory used as the write buffer, thereby enabling high-speed writing independently of the flash memory rewrite speed.
On the other hand, when data is read, if an address generated by the address generation means is given to the flash memory, it is possible to match data read rate with the host. This point is useful particularly when the operation speed of the control means in the semiconductor file system is slow compared with the host, and address generation from the control means produces a bottleneck.
The flash memory life can be prolonged by managing the erasure counts. Since the storage means required to manage the erasure counts is the volatile memory used as the write buffer, the number of parts does not increase.
The nonvolatile memory is used as a memory to store the first management information and the second management information, whereby the management information can be stored and fetched at high speed and efficiently.
On the other hand, in addition to the flash memory, inexpensive nonvolatile memory not electrically erasable is used as data memory, whereby less expensive file storage media can be provided.
If the nonvolatile memory not electrically erasable is used to store IC card information, it is made possible to be compliant with the PCMCIA specifications (standard specifications), etc. If all the above-mentioned points are implemented, the three types of memory can cover various applications and the number of parts can be reduced compared with installation of a memory for each application. Particularly in intending miniaturization for IC cards, etc., it contributes greatly to reduction of the number of parts.
According to the invention, there is further provided a flash memory system comprising a flash memory for storing data from an external system, means for temporarily storing the data from the external system upon receipt of a request to write the data into the flash memory, and a control section which stores the data in the data storage means upon receipt of the request to write the data, then transfers the data to the flash memory, wherein upon receipt of a request to read or write data from the external system before completion of transfer of the data to the flash memory, the control section interrupts the data transfer to the flash memory and responds to the request to read or write the external data.
According to the invention, there is further provided a flash memory system comprising a flash memory for storing data from an external system, means for temporarily storing the data from the external system upon receipt of a request to write the data into the flash memory, and a control section which stores the data in the data storage means upon receipt of the request to write the data, then transfers the data to the flash memory, wherein upon receipt of a new request to write data into the same address from the external system before completion of transfer of the data to the flash memory, the control section interrupts the data transfer to the flash memory and stores the new data from the external system in the data storage means and invalidates the current data being transferred to the flash memory.
According to the invention, there is provided a flash memory system comprising a flash memory for storing data from an external system, means for measuring the time required to write the data into the flash memory, means responsive to the measurement result of the write time measurement means for diagnosing a degradation degree of the flash memory, means for storing the diagnosis result offered by the degradation degree diagnosis means, and control means responsive to the diagnosis result for determining a storage location in the flash memory for the data and storing the data in the location.
As described above, the write buffer memory (data storage means) for temporarily storing data is provided for writing at high speed. The data stored in the buffer memory is transferred to the flash memory when the external system, such as the host system, does not make an access request, that is, when the flash memory system waits for the external system to make an access request. Thus, the transfer time is substantially hidden within the entire memory system. All data requested to be written from the host system is always stored in the buffer memory. Data is not directly written into the flash memory, which has a slow write speed, from the host system. Data transfer from the buffer memory to the flash memory is started upon completion of data write from the host system. The data can be transferred from the buffer memory to the flash memory until a request to access the data or another data is received from the host system, that is, while the flash memory system waits for the host system to make an access request. When receiving an access request from the host system, the controller immediately interrupts data transfer from the buffer memory to the flash memory and responds to the access request. Upon completion of processing for the request, the interrupted data transfer from the buffer memory to the flash memory is resumed at the interrupt point. As a result, writing of data from the host system into the buffer memory is completed quickly and the host system can perform the next processing without waiting for the data to be actually transferred to the flash memory, thereby improving performance of the entire flash memory system. That is, the flash memory write speed is transparent to the host system; the slow flash memory write speed can be hidden. Upon completion of processing for the access request received from the host system, the data in the buffer memory is transferred to the flash memory; the data transfer is continued until the host system makes a new access request. Therefore, the host system can interrupt the current data transfer from the buffer memory to the flash memory to make another transfer request; there is no host system wait time.
The buffer memory is provided with more than sufficient capacity to store data from the host system in the normal operating state to prevent the host system from waiting because the buffer memory overflows with data from the host system.
To reduce the data transfer time from the buffer memory to the flash memory as much as possible, when the same data as not yet transferred to the flash memory and left in the buffer memory, for example, the data in the same file, is retransferred from the host system, the current data is invalidated and the most recent data is always transferred to the flash memory. In retransmission of the same file, the old data in the file is unnecessary and may be invalidated; unnecessary data transfer need not be executed and the flash memory write count can be reduced.
To enable consecutive writing of mass data from the host system, it is also necessary to write data into the flash memory as fast as possible. However, as the flash memory is degraded, the time required for writing or erasing is prolonged, leading to slow writing. To deal with this problem, the time required for writing or erasing is measured to always be aware of how much the flash memory is degraded, and a less degraded location is selected for writing data. Shortening the write time will make it possible to prevent the buffer memory from becoming insufficient to store data in consecutive writing of mass data from the host system.
According to the invention, there is further provided a storage system having a semiconductor memory section comprising a storage section using a flash memory as a storage medium and a host system which transfers information to and from the semiconductor memory section, wherein the semiconductor memory section includes an interface circuit for transferring information to and from the host system, a control circuit for controlling a read/write of information from/into the storage section and detecting an area of the storage section where errors occur, and memory management means for retaining a used or unused state for each area of the storage section, upon detection of an error by the control circuit, for allocating an unused area as an alternate area in place of the area of the storage section where errors occur and retaining the correspondence between the allocated alternate area and the area where errors occur, and the control circuit references the memory management means for controlling a read/write of information from/into the storage section.
In this case, the control circuit can comprise information means, upon detection of an area of the storage section where errors occur, for sending error information indicating detection of the unreliable area of the storage section to the host system and the host system can comprise means for detecting receipt of the error information from the information means and means for outputting error information upon detection of receipt of the error information by the information detection means.
The semiconductor memory section may further include means for retaining predetermined error information. The control circuit, upon detection of an unreliable area of the storage section, may set error information indicating detection of the unreliable area of the storage section in the error information retention means, and the host system may comprise detection means for referencing the error information retention means for detecting the error information and means for outputting error information upon detection of the error information by the detection means. The host system can be provided with visual information means such as LED display or error message display on a CRT and voice information means with beep sound, synthetic voice, etc.
The control circuit can further detect that no alternate area becomes available in the storage section and can further set error information indicating that no alternate area becomes available in the storage section in the error information retention means.
The host system comprises input means for accepting an instruction for previously setting a data area for storing data and the alternate area of the storage section as initialization information and setting means responsive to the instruction accepted through the input means for setting the initialization information in the memory management means and the memory management means is responsive to the setting of the setting means for dividing the storage section into the data area and the alternate area for management. The memory management means comprises reallocation means for detecting an unused block of an empty area of the data area when the alternate area is not available, and reallocating the detected unused block to the alternate area and reallocation information means for informing the host system that the unused block is set as the alternate area when the block is reallocated by the reallocation means, and the host system can inhibit use of the unused block upon receipt of reallocation information from the reallocation information means.
According to the invention, there is provided a method for controlling storage in a semiconductor memory using a flash memory as a storage medium comprising the steps of previously retaining a write address corresponding to address information indicated for a write from an external system, retaining a used or unused state of an area indicated by the storage medium write address and upon receipt of a write instruction together with address information from the external system, referencing the previously retained write address corresponding to the address information, writing into the area indicated by the write address, setting the used state for the area when writing and retaining the state, determining whether or not a write error occurs during writing, if a write error occurs, allocating an unused area as an alternate area in place of the area where an error occurred and writing into the alternate area, changing the previously retained write address to a write address of the alternate area for updating the write address, and informing the external system that the alternate area is used.
According to the invention, there is provided another method for controlling storage in a semiconductor memory using a flash memory as a storage medium comprising the steps of accepting an instruction for dividing a semiconductor memory area into a data area for storing data and an alternate area, when a write error occurs, for allocating an area other than the area where the error occurred and previously retaining a write address of the data area corresponding to address information and an address of the alternate area in response to the instruction, retaining a used or unused state of the data area and the alternate area for each address, upon receipt of a write instruction together with address information, referencing the previously retained write address corresponding to the address information, writing into the area indicated by the write address, setting the used state for the area when writing and retaining the state, determining whether or not a write error occurs during the writing, if a write error occurs, allocating an unused area as an alternate area in place of the unreliable area and writing into the alternate area, changing the previously retained write address to a write address of the alternate area for updating the write address, and setting the used state for the alternate area and retaining the state.
The used or unused state for each block of the storage section is retained in the memory management means (memory block management table). When an error is detected by the control circuit, an unused block is allocated as an alternate block in place of the error incurring block of the storage section and the correspondence between the allocated alternate area and the error incurring block is retained in the memory management means or table.
To write data, the host system sends a write instruction together with address information (block identification information if data is written into each block) to the semiconductor memory section. When receiving the write instruction via the interface circuit, the control circuit of the semiconductor memory section reads the write address of the semiconductor memory section corresponding to the given address information from the memory block management table, and writes the given data into the target area (block) of the data memory. When the control circuit detects that an error occurs in the block at time of writing, the memory management means reads address information of an unused block of the alternate memory section, allocates it as an alternate block, and sets information indicating that the alternate block is used. The control circuit writes the data into the alternate block.
If an empty area for writing data when an error occurs does not exist at the write operation, the host system is informed of error information indicating detection of error incurring area of the storage section by the information means. An interrupt signal can be used as the information means. The information detection means in the host system detects receipt of the error information from the information means and the output means outputs error information when the information detection means detects receipt of the error information. If the semiconductor memory section includes the means for retaining predetermined error information, the control circuit, upon detection of an error incurring area of the storage section, sets error information indicating detection of the error incurring area of the storage section in the error information retention means. The detection means in the host system references the error information retention means for detecting the error information, and the output means outputs error information upon detection of the error information by the detection means. The control circuit may detect that no alternate area becomes available in the storage section and may set error information indicating that no alternate area becomes available in the storage section in the error information retention means. Thus, the error information can be displayed on the output means such as a CRT for informing the user that the disk does not contain any empty area, whereby the user can take proper action.
Further, the input means in the host system accepts an instruction for previously setting a data area for storing data and the alternate area of the storage section as initialization information. The setting means can be responsive to the instruction accepted through the input means for setting the initialization information in the memory management means. The memory management means may be responsive to the setting of the setting means for dividing the storage section into the data area and the alternate area for management. In this case, the memory management means comprises reallocation means for detecting an unused block of an empty area of the data area when the alternate area is not available, and reallocating the detected unused block to the alternate area and reallocation information means for informing the host system that the unused block is set as the alternate area when the block is reallocated by the reallocation means, and the host system can inhibit use of the unused block upon receipt of reallocation information from the reallocation information means.
To read data in the target block from the semiconductor disk, the semiconductor memory area corresponding to the address information for the data to be read is read from the memory management means and the data is read from the target block of the storage section. If an error occurs in the block, address information of the alternate area to the block is read from the memory management means and the data is read from the alternate area.
According to the invention, there is further provided an information processing system comprising a central processing unit, input means for inputting data, output means for outputting data, volatile storage means for storing data, nonvolatile storage means being capable of electrically rewriting stored data to which an address space accessible by the central processing unit is allocated, data control means for at least transferring data between the volatile storage means and the nonvolatile storage means, means for registering addresses of data stored in the volatile storage means by the data control means from the nonvolatile storage means in the nonvolatile storage means, and means for comparing the addresses registered in the address registration means with an address output by the central processing unit to make a data access.
When the address output by the central processing unit to make a data access is input to the address comparison means and the address comparison means makes a comparison therebetween and outputs a comparison result, the data control means determines whether or not the address is one of the addresses registered in the address registration means in response to the comparison result, and when the address is one of the registered addresses, accesses the registered address in the volatile storage means; in contrast, when the address is not any of the registered addresses, the data control means newly registers at least a predetermined range of addresses containing the address in the address registration means, newly stores data in the nonvolatile storage means corresponding to the newly registered addresses in the volatile storage means, and accesses at least one of the newly registered addresses.
Specific operation of the means will be described as an example.
To enable the CPU to directly access stored data in the flash memory not via an external I/O bus, a high-speed random access must be provided. In a direct access to the flash memory, the flash memory of random access type enables a high-speed random access like DRAM in a read access, but can be rewritten only in block units at low speed in a write access. As described above, the flash memory in the line access system, which is considered likely to become the mainstream in the future, is not adaptable to a random access even in a read access.
Then, a buffer memory which serves as a cache memory is located between the flash memory and CPU. In an optimum situation, the cache memory is made of DRAM or SRAM.
An address array for recording addresses of data stored in the cache memory and storage means for recording an access history to the cache memory are provided.
To overcome a problem of very slow flash memory rewrite compared with an access to the cache memory, an empty area is provided in the cache memory so that data at unstored addresses can always be written.
To prevent data in the main memory from being destroyed by the system careering out of control, a write protect (inhibit) flag is provided for each data area. If an attempt is made to rewrite write-protected data, the flag can be used to interrupt the CPU for warning. When the flag is rewritten, the CPU is also interrupted for warning, thereby giving double safety. After this, if the CPU does not write a predetermined code into a specific write request register, data rewrite is not enabled.
For high-speed operation, if data in the cache memory is rewritten by the CPU, the flash memory area corresponding to the data is previously erased to save the time taken to erase the flash memory area when the data is written back.
If a power supply to the system is turned off, the data in the address registration means is not lost and is retained when the power supply is again started to restart the system operation. The data in the cache memory is restored based on the data in the address registration means.
More specific description will be given.
By installing the cache memory, the demerit of the flash memory being slow in rewriting can be covered and an external interface is connected by the serial buffer for enabling a random access to the cache memory for the flash memory to which a high-speed random access cannot be made. They can be used apparently as the main memory provided with the flash memory directly connected to the CPU memory bus.
As described above, the address array for recording logical addresses of data stored in the cache memory and the storage area for recording an access history indicating oldness of data stored in the cache memory are provided whereby a determination can be made as to whether or not one address existing in the cache memory is accessed. If an address not existing in the cache memory is accessed, the access history is searched for the data least accessed since the last access occurs and the data is written back into the flash memory, the main memory to create an empty area in the cache memory in which new data is stored. This is known as a cache memory replacement algorithm.
When a data write request is received from the CPU, if the address corresponding to the data is not stored in the cache memory, large performance degradation occurs in the slow write operation flash memory if an empty area for storing the write data is created after the request is received. Then, an empty area is always reserved in t he cache memory and the data is temporarily stored in the reserved empty area. After the write data from the CPU has been transferred, a step of creating an empty area in the flash memory may be started.
Further, a write protect (inhibit) flag is provided to cope with the system careering out of control. When the flag is rewritten or an attempt is made to rewrite a write-protected area, the CPU is interrupted and responds to the interrupt with an alarm, thereby checking whether or not the CPU attempts to execute an abnormal rewrite.
If the CPU does not rewrite data into a specific register, stored data is not rewritten, thereby preventing the data in the crash occurs.
When receiving the interrupt, the CPU may execute a routine for requesting the user to determine whether or not data rewrite is to be executed. In the routine, the user determines whether or not the system careers out of control, and gives a proper instruction to the information processing system. In this case, needless to say, preferably the user can instruct the system operation to be stopped or restarted.
Referring to FIG. 98, the operation of an information processing system for implementing the configuration mentioned above is discussed. When the CPU 4101 makes a read access to the memory 4104, if cache memory block 4300 is hit, target data is read from the cache memory block 4300. If the cache memory block 4300 is miss at the read access, the CPU 4101 reads data directly from the memory 4104. Then, the data and address are retained in a new selected register in the cache memory block 4300 according to the replacement algorithm described above. If the address and data updated at the previous access are retained in the new selected register, the address and data are written back into the memory 4104, then the new data and write address are retained in the register. Since the memory 4104 is made of flash memory in the invention, if the block is not erased in writing them, the block is erased before they are written.
On the other hand, since the cache memory block 4300 of the invention is a copy back system cache, if the cache memory block 4300 is hit at a write access from the CPU 4101, only the register in the cache memory block 4300 is updated and writing into the memory 4104 is skipped. That is, data is written back into the corresponding block of the memory 4104 at later replacement. This means that the data in the corresponding block of the memory 4104 will be erased in the future. Therefore, in the invention, when the block is not yet erased, the block is previously erased. In the previous erasure process, the CPU 4101 does not immediately write into the block whose erasure is complete, and thus it need not wait for the erasure process to be completed. After this, when it becomes necessary to write data back into the block, the erasure process preceding the writing is skipped (has already been executed), shortening the access time.
If the cache memory block 4300 is miss at the write access from the CPU 4101, a new replacement target register in the cache memory block 4300 is selected and if the register is already updated, the updated data stored in the register is written back into the memory 4104, then the access address and data from the CPU 4101 are stored in the register in the cache memory block 4300. If the replacement target register is not yet updated, the register is updated. The write back process into the memory 4104 is similar to the write process into the memory 4104 when the cache memory block 4300 is miss at the read access.
Next, the operation for retaining data in the address registration means is discussed. The data stored in the cache memory is temporarily placed here so that the data can be read/written at high speed from the CPU. Since the capacity of the cache memory is limited, the data having the highest access probability and frequency from the CPU is selected and placed in the cache memory. If data not placed in the cache memory is successively accessed, system performance degrades remarkably. To prevent such an event from occurring, the cache memory structure, replacement algorithm, etc., must be optimized. However, even if they are optimized, when the data in the cache memory is lost and no data is stored in the cache memory, a miss always occurs at a read access, degrading system performance remarkably. The read access speed is slow until some degree of data is restored in the cache memory from the main memory. However, even if the data in the cache memory is lost due to power supply stop, the cache memory data can be restored to the state before the power supply stops if even comparatively small-capacity information in the address registration means is retained. The address information registered in the address registration means may be expanded in the cache memory from the main memory. One method of retaining the data in the address registration means is to retain the data in a memory with battery backup as the address registration means or to use a nonvolatile memory that can be read/written at random as the address registration means. As an alternative, when the power supply stops, the data in the address registration means is saved in a part of the main memory, which is a nonvolatile memory, or an equivalent memory, and when the power supply is restarted, the data is restored in the address registration means.